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cy7c1020d 512k (32k x 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05463 rev. *g revised april 7, 2011 features pin- and function-compatible with cy7c1020b high speed ?t aa = 10 ns low active power ?i cc = 80 ma @ 10ns low complementary metal oxide semiconductor (cmos) standby power ?i sb2 = 3 ma 2.0 v data retention automatic power-down when deselected cmos for optimum speed/power independent control of upper and lower bits available in pb-free 44-pin 400-mil wide molded soj and 44-pin thin small outline package (tsop) ii packages functional description [1] the cy7c1020d is a high-performance cmos static ram organized as 32,768 words by 16 bits. this device has an automatic power-down feature that significantly reduces power consumption when deselected. the input and output pins (io 0 through io 15 ) are placed in a high-impedance state when: deselected (ce high) outputs are disabled (oe high) bhe and ble are disabled (bhe , ble high) when the write operation is active (ce low, and we low) write to the device by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from io pins (io 0 through io 7 ), is written into the location specified on the address pins (a 0 through a 14 ). if byte high enable (bhe ) is low, then data from io pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 14 ). reading from the device by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the ?truth table? on page 9 for a complete description of read and write modes. 32k x 16 ram array io 0 ?io 7 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 sense amps data in drivers oe a 2 a 1 io 8 ?io 15 ce we ble bhe a 8 logic block diagram note 1. for guidelines on sram system design, please refer to the ?syst em design guidelines? cypress application note, available on t he internet at www.cypress.com . [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 2 of 15 contents pin configurations ............................................................ 3 selection guide ................................................................ 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics.................................................. 4 capacitance ....................................................................... 5 thermal resistance........................................................... 5 ac test loads and waveforms........................................ 5 switching characteristics................................................. 6 data retention waveform ................................................ 7 switching waveforms ...................................................... 7 truth table ........................................................................ 9 ordering information...................................................... 10 ordering code definitions ..... .................................... 10 package diagrams .......................................................... 11 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 3 of 15 pin configurations [2] 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 nc a 3 a 2 a 1 a 0 a 14 a 4 a 8 a 9 a 10 a 11 a 12 a 13 nc nc oe bhe ble ce we io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 io 8 io 9 io 10 io 11 io 12 io 13 io 14 io 15 v cc v cc v ss v ss nc 10 top view soj/tsop ii selection guide ?10 (industrial) unit maximum access time 10 ns maximum operating current 80 ma maximum cmos standby current 3 ma note 2. nc pins are not connected on the die. [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 4 of 15 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ..... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [3] ..?0.5 v to +6.0 v dc voltage applied to outputs in high z state [3] ................................. ?0.5 v to v cc + 0.5 v dc input voltage [3] .............................. ?0.5 v to v cc + 0.5 v current into outputs (low) ......................................... 20 ma static discharge voltage............................................ >2001 v (per mil-std-883, method 3015) latch-up current ...................................................... >200 ma operating range range ambient temperature v cc speed industrial ?40 c to +85 c 5 v ? 0.5 v 10 ns electrical characteristics (over the operating range) parameter description test conditions ?10 (industrial) unit min max v oh output high voltage i oh = ?4.0 ma 2.4 ? v v ol output low voltage i ol = 8.0 ma ? 0.4 v v ih input high voltage ? 2.2 v cc + 0.5v v v il input low voltage [3] ??0.50.8v i ix input load current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v i < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc 100 mhz ? 80 ma 83 mhz ? 72 ma 66 mhz ? 58 ma 40 mhz ? 37 ma i sb1 automatic ce power-down current?ttl inputs max v cc , ce > v ih v in > v ih or v in < v il , f = f max ?10ma i sb2 automatic ce power-down current?cmos inputs max v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 ?3ma note 3. v il (min) = ?2.0 v and v ih (max) = v cc + 1 v for pulse durations of less than 5 ns. [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 5 of 15 capacitance [4] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0 v 8 pf c out output capacitance 8 pf thermal resistance [4] parameter description test conditions soj tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 59.52 53.91 ? c/w ? jc thermal resistance (junction to case) 36.75 21.24 ? c/w ac test loads and waveforms [5] 90% 10% 3.0v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: ?? 3 ns fall time: ?? 3 ns 30 pf* output z = 50 ? 50 ? 1.5v (b) (a) 5v output 5 pf (c) r1 480 ? r2 255 ? high-z characteristics: including jig and scope notes 4. tested initially and after any design or process changes that may affect these parameters. 5. ac characteristics (except high-z) are tested using the load conditions shown in figure (a). high-z characteristics are teste d for all speeds using the test load shown in figure (c). [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 6 of 15 switching characteristics (over the operating range) [6] parameter description ?10 (industrial) unit min max read cycle t power [7] v cc (typical) to the first access 100 ?? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 10 ns t doe oe low to data valid ? 5ns t lzoe oe low to low z [9] 0ns t hzoe oe high to high z [8, 9] ? 5ns t lzce ce low to low z [9] 3 ? ns t hzce ce high to high z [8, 9] ? 5ns t pu [10] ce low to power-up 0 ? ns t pd [10] ce high to power-down ? 10 ns t dbe byte enable to data valid 5 ns t lzbe byte enable to low z 0 ? ns t hzbe byte disable to high z ? 5ns write cycle [11, 12] t wc write cycle time 10 ? ns t sce ce low to write end 7 ? ns t aw address set-up to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address set-up to write start 0 ? ns t pwe we pulse width 7 ? ns t sd data set-up to write end 6 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [9] 3 ? ns t hzwe we low to high z [8, 9] ? 5ns t bw byte enable to end of write 7 ? ns notes 6. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 7. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 8. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (c) of ?ac test loads and waveforms [5]? on page 5 . transition is measured when the outputs enter a high impedance state. 9. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 10. this parameter is guaranteed by design and is not tested. 11. the internal write time of the memory is defined by the overlap of ce low, we low and bhe /ble low. ce , we and bhe /ble must be low to initiate a write and the transition of these signals can terminate the write. the input data set-up and hold timing should be referenced to the lead ing edge of the signal that terminates the write. 12. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 7 of 15 data retention characteristics (over the operating range) parameter description conditions min max unit v dr v cc for data retention ? 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ? 3ma t cdr [13] chip deselect to data retention time ? 0 ? ns t r [14] operation recovery time ? t rc ? ns data retention waveform switching waveforms figure 1. read cycle no.1 (address transition controlled) [15, 16] figure 2. read cycle no.2 (oe controlled) [16, 17] 4.5v 4.5v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd t dbe t lzbe t hzce i cc high impedance i sb oe ce address data out v cc supply bhe ,ble current notes 13. tested initially and after any design or proce ss changes that may affect these parameters. 14. full device operation requires linear v cc ramp from v dr to v cc(min) > 50 ? s or stable at v cc(min) > 50 ? s. 15. device is continuously selected. oe , ce , bhe and/or ble = v il . 16. we is high for read cycle. 17. address valid prior to or coincident with ce transition low. [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 8 of 15 figure 3. write cycle no. 1 (ce controlled) [18, 19] figure 4. write cycle no. 2 (ble or bhe controlled) [18, 19] switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw t data io address ce we bhe ,ble t hd t sd t bw t sa t ha t aw t pwe t wc t sce data io address bhe ,ble we ce notes 18. data io is high impedance if oe or bhe and/or ble = v ih . 19. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 9 of 15 figure 5. write cycle no. 3 (we controlled, oe low) [20, 21] truth table ce oe we ble bhe io 0 ?io 7 io 8 ?io 15 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high z read ? lower bits only active (i cc ) h l high z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high z write ? lower bits only active (i cc ) h l high z data in write ? upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc ) notes 20. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd. 21. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data io address ce we bhe ,ble [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 10 of 15 ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1020d-10vxi 51-85082 44-pin (400-mil) molded soj (pb-free) industrial CY7C1020D-10ZSXI 51-85087 44-pin tsop type ii (pb-free) ordering code definitions please contact your local cypress sales repr esentative for availability of these parts. temperature range: i = industrial package type: xxx = vx or zsx vx = 44-pin molded soj (pb-free) zsx = 44-pin tsop type ii (pb-free) speed: 10 ns d = c9, 90 nm technology 0 = data width 16-bits 02 = 512-kbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - 10 xxx 7 02 i d 0 [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 11 of 15 package diagrams figure 6. 44-pin (400-mil) molded soj, 51-85082 51-85082 *c [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 12 of 15 figure 7. 44-pin thin small outline package type ii, 51-85087 all product and company names mentioned in this document may be the trademarks of their respective holders. package diagrams (continued) 51-85087 *c [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 13 of 15 acronyms document conventions units of measure acronym description bga ball grid array cmos complementary metal oxide semiconductor fbga very fine ball gird array i/o input/output tsop thin small outline package sram static random access memory ttl transistor transistor logic symbol unit of measure c degrees celsius ? a microamperes ma milliampere mhz megahertz ns nanoseconds pf picofarads v volts ? ohms w watts [+] feedback
cy7c1020d document #: 38-05463 rev. *g page 14 of 15 document history page document title: cy7c1020d, 512k (32k x 16) static ram document #: 38-05463 rev. ecn no. issue date orig. of change description of change ** 201560 see ecn swi advance data sheet for c9 ipp *a 233695 see ecn rkf 1) dc parameters modified as per eros (spec # 01-0216) 2) pb-free offering in the ?ordering information? *b 263769 see ecn rkf 1) corrected pin #18 on soj/tsopii pinout (page #1) from a 15 to a 4 2) changed io 1 - io 16 to io 0 - io 15 on the pin-out diagram 3) added t power spec in switching characteristics table 4) added data retention characteristics table and waveforms 5) shaded ?ordering information? *c 307594 see ecn rkf reduced speed bins to ?10, ?12 and ?15 ns *d 560995 see ecn vkn converted from preliminary to final removed commercial operating range removed 12 ns speed bin added i cc values for the frequencies 83mhz, 66mhz and 40mhz updated thermal resistance table updated ordering information table changed overshoot spec from v cc +2v to v cc +1v in footnote #3 *e 802877 see ecn vkn changed i cc specs from 60 ma to 80 ma fo r 100mhz, 55 ma to 72 ma for 83mhz, 45 ma to 58 ma for 66mhz, 30 ma to 37 ma for 40mhz *f 3109992 12/14/2010 aju added ordering code definitions . updated package diagrams . *g 3219056 04/07/2011 pras added toc added acronyms and units of measure table. updated datasheet as per template. [+] feedback
document #: 38-05463 rev. *g revised april 7, 2011 page 15 of 15 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1020d ? cypress semiconductor corporation, 2010-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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